Testing for parametric faults in static CMOS circuits
نویسندگان
چکیده
Many defects causing bridges, breaks, and transistor stuck-ons in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. These undetected, non-traditional faults may be detected as increased propagation time or as excessive quiescent power supply current (I DDQ). In this paper we compare the cost of testing for excess I DDQ caused by bridge, break and transistors stuck-on faults versus the cost of traditional testing methods.
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